1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a highly integrated semiconductor memory device having a capacitor over bit-line (COB) cell structure, and to a method for manufacturing the same.
2. Description of the Related Art
As semiconductor memory devices such as dynamic random access memories (DRAMs) become more highly integrated, it is very important to develop a process for increasing their cell capacitance and securing a process margin for forming a fine metal interconnection. In general, a surface step is formed between a cell array region, where a storage electrode is formed, and a peripheral circuit region for driving the cells. In the process of forming these metal interconnections on a substrate where the surface step is formed, a technology for uniformly forming a metal interconnection in the cell array region and the peripheral circuit region is very important.
In particular, in highly integrated 256 M-bit DRAMs and above, the height of the storage electrode of the capacitor is increased to 1 xcexcm in order to secure cell capacitance. At this time, a step generated between the cell array region and the peripheral circuit region is also formed at a height of 1 xcexcm . Thus, it is very difficult to uniformly form a metal interconnection over the cell region and the peripheral circuit region even after a subsequent process of planarization.
FIG. 1 is a sectional view of a conventional DRAM device.
Referring to FIG. 1, reference numeral 10 denotes a semiconductor substrate; reference numeral 12 denotes a word line acting as a gate electrode of an access transistor formed in a cell array region; reference numeral 13 denotes a first interdielectric layer covering the access transistor; reference numeral 14 denotes a bit line connected to a source region (or drain region) of the access transistor; reference numeral 16 denotes a second interdielectric layer covering the surface of the resultant structure where the bit line 14 is formed; reference character C1 denotes a storage electrode connected to the drain region (or source region) of the access transistor; reference character C2 denotes a plate electrode covering the cell array region of the resultant structure where the storage electrode C1 is formed; reference numeral 18 denotes a third interdielectric layer covering a cell array region and a peripheral circuit region of the resultant structure where the plate electrode C2 is formed; and reference numeral 20 denotes a metal interconnection formed on the third inter dielectric layer 18.
As described above, in the conventional memory device, a COB structure is widely used to obtain sufficient cell capacitance. That is, in order to form a high performance capacitor, a COB structure where a three-dimensional cell capacitor is formed on a semiconductor substrate over a bit line, is widely employed in DRAM devices. However, although increasing the height of the storage electrode formed in a restricted unit cell area allows the desired cell capacitance to be obtained, it also increases a step xe2x80x9chxe2x80x9d between the cell array region and the peripheral circuit region, as shown in FIG. 1. Thus, if photoresist is coated on the third interdielectric layer by a spin coating method, there is a large difference in the thickness of the photoresist layer between the cell array region and a peripheral circuit region. This reduces a focus margin during a photo-lithography process, and a photoresist pattern having abnormal profile is formed in the cell array region and the peripheral circuit region. Accordingly, it is difficult to normally etch using the photoresist pattern as an etching mask, because the photoresist pattern has an abnormal profile.
In order to reduce the step between the cell array region and the peripheral circuit region, there is a method for excessively planarizing the third interdielectric layer. However, in this case the depth of a metal contact hole formed by etching the first through third interdielectric layers is increased. As a result, it is more difficult to improve the reliability of the metal interconnection filling the metal contact hole.
To solve the above problems, it is an objective of the present invention to provide a highly integrated semiconductor memory device having a larger process margin during photolithography and etch process for forming a subsequent metal interconnection, due to a slow gradient between a cell array region and a peripheral circuit region.
It is another objective of the present invention to provide a method of manufacturing the highly integrated semiconductor memory device.
Accordingly, to achieve the first objective, a semiconductor memory device is provided having a cell array region and a peripheral circuit region, wherein the cell array region comprises: a plurality of cell storage electrodes, a plurality of dummy storage electrodes arranged at a periphery of the cell array region to surround the plurality of cell storage electrodes, and plate electrode formed over the plurality of cell storage electrodes and the plurality of dummy storage electrodes, wherein an outermost sidewall of each dummy storage electrode adjacent to the peripheral circuit region has an inclined profile.
Preferably, the dummy storage electrode is formed of the same material as the cell storage electrode, and the angle of inclination of the outermost sidewall of the dummy storage electrode is 40xc2x0xcx9c70xc2x0.
The cell array region includes a semiconductor substrate having an access transistor comprising a source region electrically connected to the cell storage electrode, a drain region spaced apart from the source region, a channel region interposed between the source region and the drain region, an insulating layer formed over the channel region, and a gate electrode formed over the insulating layer; and a bit line electrically connected to the drain region of the access transistor,
Preferably, the outmost sidewalls of the dummy storage electrodes, facing toward the outside of the cell array region, are inclined. The gradient of the sidewalls of the dummy storage electrodes is preferably 40xc2x0xcx9c70xc2x0.
To achieve the second objective, a plurality of cell storage electrodes are formed over a semiconductor substrate in the cell array region. A plurality of dummy storage electrodes are then formed over the semiconductor substrate in the cell array region, and around the plurality of cell storage electrodes. The dummy storage electrodes have dummy sidewalls of an inclined profile facing toward the peripheral circuit region and formed. Then, a plate electrode is formed in the cell array region over the plurality of cells storage electrodes and over the plurality of dummy storage electrodes.
In more detail, a first interdielectric layer is formed in a cell array region where a plurality of access transistors are formed and in a peripheral circuit region where a plurality of peripheral circuit transistors are formed. The first interdielectric layer is patterned to form a plurality of bit line contact holes exposing source regions (or drain regions) of the access transistors, and a plurality of bit lines covering the plurality of contact holes are formed. A second interdielectric layer is formed on the entire surface of the semiconductor substrate where the plurality of bit lines are formed, and the second interdielectric layer and the first interdielectric layer are patterned to form a plurality of storage contact holes exposing drain regions (or source regions) of the access transistors. A plurality of storage electrodes covering the storage contact holes are formed in the cell array region. At this time, outmost storage electrodes, i.e., a dummy storage electrodes positioned at the edges of the cell array region, are formed in a shape different from the cell storage electrode. In other words, the sidewall of the dummy storage electrode facing toward the peripheral circuit region is inclined. A dielectric layer and a plate electrode are formed in sequence in a cell array region where the plurality of storage electrodes are formed. Actually, no information is stored in the dummy storage electrode. The dummy storage electrode is formed to merely alleviate the loading effect, to thereby improve the pattern uniformity of all cell storage electrodes.
A conductive layer filling the storage contact hole, e.g., a doped polysilicon layer, is formed on the entire surface of the semiconductor substrate where a plurality of storage contact holes are formed, in order to form the dummy storage electrodes having the inclined sidewalls. A plurality of photoresist patterns are formed on the conductive layer of the cell array region. Spacers are formed on the sidewalls of the photoresist patterns. A first dry etching process is performed to a predetermined depth using the spacers and the photoresist patterns as an etching mask. The first dry etching process is performed using, a predetermined etching gas, e.g., Cl2 gas and N2 gas. At this time, a material of the conductive layer etched by the Cl2 gas, i.e., polysilicon, reacts with the photoresist patterns to generate polymers. The polymers are mostly generated by the peripheral circuit region. This is because the exposed area of the conductive layer in the peripheral circuit region is wider than that in the cell array region. Thus, a great deal of polymers adhere to the sidewall of the stepped portion of the conductive layer formed by the first dry etching process, adjacent to the peripheral circuit region. The photoresist patterns are eliminated and cylindrical storage electrodes are formed by performing a second dry etching process, etching a conductive layer using the spacers as an etching mask until the second interdielectric layer is exposed.
At this time, the second dry etching process is performed using Cl2 gas and N2 gas. By the second dry etching process, the sidewalls of the cell storage electrodes are formed vertically, and the outer sidewalls of the dummy storage electrodes are formed with a slope. This is caused by polymers generated by the first dry etching process adhering to the sidewalls of the conductive layer. Preferably, the gradient of the inclined sidewalls is 40xc2x0xcx9c70xc2x0.